ABOUT THE AUTHORS  

Sung-Mo “Steve” Kang received his PhD in electrical engineering from the University of California, Berkeley. He has worked on the development of full- custom CMOS VLSI chips, including the world’s rst 32-bit full CMOS micro- processor and peripheral chips at AT＆T Bell Laboratories in Murray Hill, New Jersey. He has taught digital integrated circuits at the University of Illinois at Urbana-Champaign; the University of California, Santa Cruz; the University of California, Merced; and the Korea Advanced Institute of Science and Technology (KAIST) in Daejeon, Korea. He has also given invited lectures and tutorials on CMOS digital circuits, reliability, and computer-aided design of VLSI circuits and systems at major conferences and universities globally.
Dr. Kang is a fellow of IEEE, ACM, and AAAS and has received many awards, including the IEEE Millennium Medal, IEEE Graduate Teaching Technical Field Award, IEEE CAS Society M. E. Van Valkenburg Award, IEEE CAS Society Tech- nical Excellence Award, SRC Technical Excellence Award, and Chang-Lin Tien Education Leadership Award. He has served as Department Head of the University of Illinois at Urbana-Champaign; Dean of Engineering at the University of California, Santa Cruz; Chancellor of the University of California, Merced; and President of KAIST, Daejeon, Korea.

Yusuf Leblebici received a PhD in electrical and computer engineering from the University of Illinois at Urbana-Champaign. He has been a visiting assistant profes- sor of electrical and computer engineering at the University of Illinois at Urbana- Champaign, associate professor of electrical and electronics engineering at Istanbul Technical University, and associate professor of electrical and computer engineering at Worcester Polytechnic Institute. He also served as the microelectronics program coordinator at Sabanci University. Currently, he is a full (chair) professor at the Swiss Federal Institute of Technology in Lausanne, Switzerland, and director of the Microelectronic Systems Laboratory. His research interests include design of high- performance CMOS digital and mixed-signal integrated circuits, computer-aided design of VLSI systems, intelligent sensor interfaces, modeling and simulation of semiconductor devices, and VLSI reliability analysis. He is a fellow of IEEE and re- cipient of the NATO Science Fellowship Award, the Young Scientist Award of the Turkish Scientic and Technological Research Council, and the Joseph Samuel Satin Distinguished Fellow Award of the Worcester Polytechnic Institute. He was elected as Distinguished Lecturer of the IEEE Circuits and Systems Society for 2010–2011.

Chulwoo Kim received BS and MS degrees in  electronics  engineering  from Korea University, and a PhD in electrical and computer engineering from the Uni- versity of Illinois at Urbana-Champaign. In 1999, he worked as a summer intern at Design Technology at Intel Corporation, Santa Clara, California. In May 2001, he joined IBM Microelectronics Division in Austin, Texas, where he was involved in cell processor design. Since September 2002, he has been with the Department of Elec- tronics and Computer Engineering at Korea University, where he is currently a pro- fessor. He was a visiting professor at the University of California, Los Angeles and at the University of California, Santa Cruz. His current research interests are in the areas of wireline transceiver, memory, power management, and data converters.
Dr. Kim received the Samsung HumanTech Thesis Contest Bronze Award, the ISLPED Low-Power Design Contest Award, the DAC Student Design Contest Award, the SRC Inventor Recognition Award, the Young Scientist Award from the Ministry of Science and Technology of Korea, the Seoktop Award for excellence in teaching, and the ASP-DAC Best Design Award. He is currently on the editorial board of IEEE Transactions on VLSI Systems and on the Technical Program Com- mittee of the IEEE International Solid-State Circuits Conference.
 
作 者 简 介 

Sung-Mo (Steve) Kang（康松默） 于美国加州大学伯克利分校电机工程系取得博士 学位，主要研究全定制 CMOS VLSI 芯片的发展。在美国新泽西州默里山 AT＆T 贝尔实验 室，他研究出了世界上第一个 32 位全 CMOS 微处理器及外围芯片。他曾在美国伊利诺伊 大学厄巴纳 - 香槟分校、美国加州大学圣克鲁兹分校、美国加州大学默塞德分校以及韩国 科学技术院（位于韩国大田）教授数字集成电路课程。他还在全球一些主要的会议和大学 中，关于 CMOS 数字电路、可靠性，以及电脑辅助 VLSI 电路和系统的设计等问题，发表 特约演讲及担任特邀讲师。
Kang 教授是 IEEE、ACM 以及 AAAS 会员。曾获诸多奖项，包括 IEEE Millennium 奖、 IEEE 研究生教育技术领域奖、IEEE 电路与系统协会 M. E. Van Valkenburg 奖、 IEEE 电路 与系统协会技术成就奖、SRC 卓越技术奖以及 Chang-Lin Tien 教育领导奖。他曾在美国伊 利诺伊大学厄巴纳 - 香槟分校任系主任，美国加州大学圣克鲁兹分校任工程系系主任，美 国加州大学默塞德分校担任名誉校长，现在在韩国科学技术院担任院长。

Yusuf Leblebici 于美国伊利诺伊大学厄巴纳 - 香槟分校电机和计算机工程系取得博士学 位，是美国伊利诺伊大学厄巴纳 - 香槟分校的客座副教授，土耳其伊斯坦布尔科技大学电 机和电子工程系的副教授，美国伍斯特理工学院电机和计算机工程系的副教授。曾担任土 耳其萨班哲大学微电子项目的协调人。目前，他是瑞士联邦理工学院的全职（主）教授， 并兼任微电子系统实验室主任。主要研究高性能 CMOS 数字及混合信号的集成电路设计， VLSI 系统的计算机辅助设计，智能传感器接口，半导体器件的模型及仿真，以及 VLSI 可 靠性分析。他是 IEEE 会士，获北大西洋公约组织科学研究会奖，土耳其科学技术委员会年 轻科学家奖，美国伍斯特理工学院 Joseph Samuel Satin 杰出人物奖。曾被选为 IEEE 电路与 系统协会 2010-2011 年度杰出演讲人。

Chulwoo Kim 于韩国高丽大学电子工程系取得理科学士学位和硕士学位，于美国伊 利诺伊大学厄巴纳 - 香槟分校电机和计算机工程系取得博士学位。1999 年，曾在美国加利 福尼亚州圣克拉拉的因特尔公司设计工艺部门进行暑假实习；2001 年 5 月，加入位于得 克萨斯州奥斯汀的 IBM 微电子部，研究单元处理器设计；2002 年 9 月，加入韩国高丽大
 
学电子和计算机工程系，现成为该系教授。曾任美国加州大学洛杉矶分校和美国加州大学 圣克鲁兹分校的客座教授。目前研究有线线路收发器、存储器、功率管理以及转换器。
Kim 教授曾获三星人机工程论文比赛铜奖，ISLPED 低功率设计比赛奖，DAC 学生 设计比赛奖，SRC 发明家奖，韩国科学技术部青年科学家奖，Seokto 优秀教师奖，ASP- DAC 最佳设计奖。现任 IEEE VLSI 系统交流会编委会委员及 IEEE 固体电路国际会议科技 项目委员会成员。
 
PREFACE 

Complementary metal oxide semiconductor (CMOS) digital integrated circuits are the enabling technology for the modern information age. Because of their intrinsic features in low-power consumption, large noise margins, and ease of design, CMOS integrated circuits have been widely used to develop random access memory (RAM) chips, microprocessor chips, digital signal processor (DSP) chips, and application-specic integrated circuit (ASIC) chips. The popular use of CMOS cir- cuits continues to grow with the increasing demands for low-power, low-noise inte- grated electronic systems in the development of mobile computing platforms, wearable communication devices, smart phones, and multimedia systems.
Since the eld of CMOS integrated circuits is broad, it is conventionally divided into digital CMOS circuits and analog CMOS circuits. This textbook is focused on the CMOS digital integrated circuits. However, it should be noted that the boundary between classical digital and analog CMOS design is becoming increasingly blurred, especially with the challenges presented by nanometer-scale fabrication technolo- gies, very low operating voltages, and operating frequencies extending well into the multi-GHz range. Therefore, we attempt to present the analysis and design of digital CMOS integrated circuits from an “analog” point-of-view, i.e., taking into account the analog, non-discrete nature of the devices and circuits that are used to implement digital functions.
The origins of this textbook date back to the early 1990s, when the rst two authors were intensively involved in undergraduate- and graduate-level teaching of digital IC fundamentals. At the University of Illinois at Urbana-Champaign, where both of us were teaching at the time, we tried some of the available textbooks on digital MOS integrated circuits for our senior-level technical elective course, ECE382—Large Scale Integrated Circuit Design. Students and instructors alike realized, however, that there was a need for a new book with more comprehensive treatment of CMOS digital circuits. Thus, our textbook project was initiated several years ago by assembling our own lecture notes. Since 1993, we have used evolving versions of this material at the University of Illinois at Urbana-Champaign, at Istanbul Technical University, at Worcester Polytechnic Institute, and at the Swiss Federal Institute of Technology in Lausanne. We are both encouraged by comments from our students, colleagues, and re- viewers. The rst edition of CMOS Digital Integrated Circuits: Analysis and Design was published in late 1995.
Soon after publishing the rst edition, we saw the need for updating it to reect the many constructive comments we were receiving from instructors and students who used the textbook. We intended to include and update important topics such as low-power circuit design and interconnects in high-speed circuit design, as well as the deep sub- micron circuit design issues, and to provide more rigorous treatment of new develop- ments in memory circuits. We also felt that in a rapidly developing eld such as CMOS digital circuits, the quality of a textbook can only be preserved by timely updates re- ecting the state of the art. This realization has led us to embark on the successive revi- sions of our work, with the second edition appearing in 1998 and the third edition in 2002, to reect the advances in technology and in circuit design practices.
During the 11 years that have passed since the publication of the third edition in 2002, the domain of CMOS digital integrated circuits has continued to grow and develop at an ever-increasing pace. The advent of nanometer-scale technologies and the widespread use of system-on-chip architectures combining a large number of functional blocks on chip have ushered in dramatic changes in the way digital CMOS integrated circuit design has to be treated. Thus, we came to the conclusion that in- cremental revisions would no longer do justice for the next edition of this textbook, and that we needed a comprehensive rewriting of virtually all chapters. The author team was expanded by the valuable addition of Professor Chulwoo Kim of Korea University, and an extensive revision was embarked upon. The fourth edition is the outcome of this intensive effort.
CMOS Digital Integrated Circuits: Analysis and Design is intended primarily as a comprehensive textbook at the senior level and rst-year graduate level, as well as a reference for practicing engineers in the areas of integrated circuit design, digi- tal design, and VLSI. Recognizing that the area of digital integrated circuit design is evolving at an increasingly faster pace, we have made our best effort to present up- to-date materials on all subjects covered. This textbook contains 15 chapters; we recognize that it would not be possible to cover rigorously all of this material in one semester. Thus, we would propose the following based on our teaching experience: At the undergraduate level, coverage of the rst 10 chapters would constitute suf- cient material for a one-semester course on CMOS digital integrated circuits.
Time permitting, some selected topics in Chapter 11, “Low-Power CMOS Logic Circuits,” Chapter 12, “Arithmetic Building Blocks,” and Chapter 13, “Clock and I/O Circuits” could also be covered. Alternatively, this book could be used for a two- semester course, allowing a more detailed treatment of advanced issues, which are presented in the later chapters. At the graduate level, selected topics from the rst 10 chapters plus the last 5 chapters can be covered in one semester.
The rst 8 chapters of this textbook are devoted to a detailed treatment of the MOS transistor with all its relevant aspects; to the static and dynamic operation prin- ciples, analysis, and design of basic inverter circuits; and to the structure and opera- tion of combinational and sequential logic gates. Note that the introduction chapter has been signicantly expanded to include a detailed presentation of VLSI design methodologies. Since the digital integrated circuit design techniques discussed in the rst half of this textbook are directly relevant for digital VLSI and ASIC design, we felt that the context should be presented at the beginning of the book. The issues of on-chip interconnect modeling and interconnect delay calculation are covered exten- sively in Chapter 6, which provides a complete view of switching characteristics in digital integrated circuits. A separate chapter (Chapter 9) has been reserved for the treatment of dynamic logic circuits, which are used in state-of-the-art VLSI chips. Chapter 10 has been completely revised in both content and presentation; it offers an in-depth presentation of many state-of-the-art semiconductor memory circuits.
Recognizing the increasing importance of low-power circuit design, we dedicate one chapter (Chapter 11) to low-power CMOS logic circuits, which provides a com- prehensive coverage of methodologies and design practices that are used to reduce the power dissipation of large-scale digital integrated circuits. Key arithmetic build- ing blocks are presented in Chapter 12, with an emphasis on high-performance multi- bit adders and multipliers.
Next, Chapter 13 provides a clear insight into the important subjects of clocking and chip I/O design. Critical issues such as ESD protection, clock distribution, clock buffering, and latch-up phenomena are discussed in detail. Finally, the more advanced but important topics of design for manufacturability and design for testability are covered in Chapters 14 and 15, respectively.
We have long debated the coverage of nMOS circuits in this textbook. We have concluded that some coverage should be provided for pedagogical reasons. Thus, to emphasize the load concept, which is still widely used in many areas in digital circuit design, we present basic resistive-load and pseudo-nMOS inverter circuits along with their CMOS counterparts in Chapter 5, while we present pseudo-nMOS logic gates (NAND/NOR) in Chapter 7.
The Online Learning Center for this edition (www.mhhe.com/kang) also contains:

■ An Instructors Manual
■ Lecture Slides (PowerPoint and PDF)
■ Cadence Design Tutorial
■ Color Plates.

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Although an immense amount of effort and attention to detail were expended to prepare the camera-ready manuscript, this textbook may still have some aws and
mistakes due to erring human nature. We welcome and greatly appreciate suggestions and corrections from readers for the improvement of technical content as well as the presentation style.

ACKNOWLEDGMENTS TO THE FIRST EDITION

Our colleagues have provided many constructive comments and encouragement for the completion of the rst edition. Professor Timothy N. Trick, former head of the department of electrical and computer engineering at the University of Illinois at Urbana-Champaign, has strongly supported our efforts from the very beginning. The appointment of Sung-Mo Kang as an associate in the Center for Advanced Study at the University of Illinois at Urbana-Champaign helped to start the process. Yusuf Leblebici acknowledges the full support and encouragement from the department of electrical and electronics engineering at Istanbul Technical University, where he introduced a new digital integrated circuits course based on the early version of this book and received very valuable feedback from his students.
Yusuf Leblebici also thanks the ETA advanced Electronics Technologies Re- search and Development Foundation at Istanbul Technical University for their gen- erous support. Professor Elyse Rosenbaum and Professor Resve Saleh used the early versions of the manuscript as the textbook for ECE382 at Illinois and provided many helpful comments and corrections, which have been fully incorporated with deep appreciation. Professor Elizabeth Brauer, currently at Northern Arizona University, has also done the same at the University of Kentucky.
The authors would like to express sincere gratitude to Professor Janak Patel of the University of Illinois at Urbana-Champaign for generously mentoring the authors in writing Chapter 15, “Design for Testability.” Professor Patel has provided many constructive comments, and many of his expert views on the subject are reected in this chapter. Professor Prith Banerjee of Northwestern University and Professor Farid Najm of the University of Illinois at Urbana-Champaign also provided many good comments. We would also like to thank Dr. Abhijit Dharchoudhury for his in- valuable contribution to Chapter 14, “Design for Manufacturability.”
Professor Duran Leblebici of Istanbul Technical University, who is the father of the second author, reviewed the entire manuscript in its early development phase, and provided very extensive and constructive comments, many of which are reected in the nal version. Both authors gratefully acknowledge his support during all stages of this venture. We also thank Professor Cem G＆ouml;knar of Istanbul Technical University, who offered very detailed and valuable comments on “Design for Testability,” and Professor Ug＆#732; ur ＆Ccedil;ilingirog＆#732; lu of the same university, who offered many excellent suggestions for improving the manuscript, especially the chapter on semiconductor memories.
Many of the authors’ former and current students at the University of Illinois at Urbana-Champaign also helped in the preparation of gures and verication of circuits using SPICE simulations. In particular, Dr. James Morikuni, Dr. Weishi Sun, Dr. Pablo Mena, Dr. Jaewon Kim, Mr. Steve Ho, and Mr. Sueng-Yong Park deserve recognition. Ms. Lilian Beck and the staff members of the Publications Ofce in the department of electrical and computer engineering at the University of Illinois at Urbana-Champaign read the entire manuscript and provided excellent editorial comments.
The authors would also like to thank Dr. Masakazu Shoji of AT＆T Bell Labora- tories, Professor Gerold W. Neudeck of Purdue University, Professor Chin-Long Wey of Michigan State University, Professor Andrew T. Yang of the University of Washington, Professor Marwan M. Hassoun of Iowa State University, Professor Charles E. Stroud of the University of Kentucky, Professor Lawrence Pileggi of the University of Texas at Austin, and Professor Yu Hen Hu of the University of Wisconsin at Madison, who read all or parts of the manuscript and provided many valuable comments and encouragement.
The editorial staff of McGraw-Hill has been an excellent source of strong support from the beginning of this textbook project. The venture was originally initiated with the enthusiastic encouragement from the previous electrical  engineering  editor, Ms. Anne (Brown) Akay. Mr. George Hoffman, in spite of his relatively short associ- ation, was extremely effective and helped settle the details of the publication planning.
During the last stage, the new electrical engineering editor, Ms. Lynn Cox, and Mr. John Morriss, Mr. David Damstra, and Mr. Norman Pedersen of the editing department were superbly effective and we enjoyed dashing with them to nish the last mile.

ACKNOWLEDGMENTS TO THE SECOND EDITION

The authors are truly indebted to many individuals who, with their efforts and their help, made the second edition possible. We would like to thank Dr. Wolfgang Fichtner, President and CEO of ISE Integrated Systems Engineering, Inc., and the technical staff of ISE in Zurich, Switzerland, for providing computer-generated cross-sectional color graphics of MOS transistors and CMOS inverters, which are featured in the color plates. The rst author acknowledges the support provided by the U.S. Senior Scientist Research Award from the Alexander von Humbold Stiftung in Germany, which was very helpful for the second edition. The appointments of the second author as Associ- ate Professor at Worcester Polytechnic Institute and as Visiting Professor at the Swiss Federal Institute of Technology in Lausanne, Switzerland have provided excellent en- vironments for the completion of the revision project. The second author also thanks Professor Daniel Mlynek of the Swiss Federal Institute of Technology in Lausanne for his continuous encouragement and support. Many of the authors’ former and current students at the University of Illinois at Urbana-Champaign, at the Swiss Federal Insti- tute of Technology in Lausanne, and at Worcester Polytechnic Institute also helped in the preparation of gures and verication of circuits using SPICE simulations. In par- ticular, Dr. James Stroming and Mr. Frank K. Gürkaynak deserve special recognition for their extensive and valuable efforts.
The authors would also like to thank Professor Charles Kime of the University of Wisconsin at Madison, Professor Gerold W. Neudeck of Purdue University, Professor D. E. Ioannou of George Mason University, Professor Subramanya Kalkur of the Uni- versity of Colorado, Professor Jeffrey L. Gray of Purdue University, Professor Jacob Abraham of the University of Texas at Austin, Professor Hisham Z. Massoud of Duke University, Professor Norman C. Tien of Cornell University, Professor Rod Beresford of Brown University, Professor Elizabeth J. Brauer of Northern Arizona University, Professor Reginald J. Perry of Florida State University, and Professor Cem G＆ouml;knar of Istanbul Technical University who read all or parts of the revised manuscript and provided their valuable comments and encouragement.
The editorial staff of McGraw-Hill has, as always, been wonderfully supportive from the beginning of the revision project. We thankfully recognize the contributions of our previous electrical engineering editor, Ms. Lynn Cox, and we appreciate the extensive efforts of Ms. Nina Kreiden, who helped the project get off the ground in its early stages. During the nal stages of this project, Ms. Kelley Butcher, Ms. Karen Nelson, and Mr. Francis Owens were extremely effective and helpful, and we enjoyed sharing this experience with them.

ACKNOWLEDGMENTS TO THE THIRD EDITION

Several individuals have contributed their time and efforts to the third edition of our textbook. The authors would like  to  acknowledge  the  invaluable  contribution  of Dr. Seung-Moon Yoo who was instrumental in the extensive revision of the Memory chapter (Chapter 10). His technical insight, his meticulous attention to detail, and his very productive work are truly appreciated. The rst author acknowledges the University of California at Santa Cruz for valuable support in his new position as Dean of the School of Engineering, and for enabling him to concentrate on the revision of the manuscript. The appointment of the second author as Full Professor at the Swiss Federal Institute of Tech- nology in Lausanne, Switzerland, has also provided an excellent environment for the completion of the project. The second author gratefully acknowledges Mme. Séverine Eggli for her valuable assistance in revisions, and for typing sections of the text. The au- thors thank Mr. Tom Vernier and the technical staff of the MOSIS organization for gener- ously providing the SPICE BSIM parameters for the TSMC 0.18 mm process that were extracted by MOSIS. The authors also acknowledge Dr. Michael W. Davidson of the Florida State University National High Magnetic Field Laboratory, for providing the DEC Alpha chip microphotographs that appear on the cover.
The authors would like to thank the following individuals who read all or parts of the revised manuscript and provided their valuable comments and encouragement.
Professor Massoud Pedram, University of Southern California
Professor Eby G. Friedman, University of Rochester Professor Chien-In Henry Chen, Wright State University Professor Ivan Kourtev, University of Pittsburgh Professor Dimitris E. Ioannou, George Mason University
Professor Thottam S. Kalkur, University of Colorado at Colorado Springs
Professor Yong-Bin Kim, Northeastern University Professor Pratapa Reddy, Rochester Institute of Technology Professor Hisham Z. Massoud, Duke University
Professor Resve A. Saleh, University of British Columbia
Professor Simon Foo, Florida State University
Professor David W. Parent, San Jose State University
Professor Jaime Ramirez-Angulo, New Mexico State University
Professor Nur Touba, University of Texas at Austin
Professor Nicholas C. Rumin, McGill University
The editorial staff of McGraw-Hill has again been very helpful and supportive through- out the entire revision project. This project started with the insightful initiative of Mr. Tom Casson, our publisher at McGraw-Hill. We would like to acknowledge his valuable sup- port and encouragement. We thankfully recognize the contributions of Ms. Michelle Flomenhoft, Ms. Betsy Jones, and Ms. Rose Koos. We especially thank them for their helpful assistance during all stages of this complex project, and for their patience and per- sistence. We also acknowledge Mr. Rick Noel for creating the cover design of the third edition. We truly enjoyed sharing this experience with the entire McGraw-Hill team.

ACKNOWLEDGMENTS TO THE FOURTH EDITION

Perhaps more pronounced than in the previous editions, this fourth edition has bene- ted from the valuable contributions of a number of colleagues and co-workers. As in the third edition, Dr. Seung-Moon Yoo has played a key role in the extensive revision of the Memory chapter (Chapter 10). His technical insight, his meticulous attention to detail, and his productive work are truly appreciated. The rst author acknowledges the University of California system for its support for administrative leave, which en- abled focused effort for the revision, and many colleagues in the Department of Elec- trical Engineering at the Korea Advanced Institute of Science and Technology (KAIST) who encouraged and supported the nal phase of this revision.
The second author acknowledges the Swiss Federal Institute of Technology in Lausanne, Switzerland, for providing an excellent environment for the completion of the project. The third author acknowledges the Korea University in Seoul, Korea, for enabling him to nish the revision.
A number of students at Korea University helped in the preparation of gures, SPICE simulations, and layout. Special recognition goes to Dr. Young-Ho Kwak, Dr. Phi-Hung Pham, Dr. Moo-Young Kim, Dr. Inhwa Jung, Dr. Minyoung Song, Mr. Hokyu Lee, Mr. Jungmoon Kim, Mr. Junyoung Song, and Mr. Sewook Hwang.
The authors thank Professor Rhett Davis at North Carolina State University for let- ting us use freePDK45TM for layout and Professor Yu Cao at Arizona State University for PTM SPICE BSIM parameters for 65-nm process (http://ptm.asu.edu/). We devel- oped our own parameters based on that and used it for simulations in this textbook.
The authors would like to thank the following individuals who read all or parts of the revised manuscript and provided their valuable comments and encouragement.
Khalid H. Abed, Jackson State University
Erik Cheever, Swarthmore College
Frank T. Duda Jr., Grove City College
Kaliappan Gopalan, Purdue University–Calumet
Yong-Bin Kim, Northeastern University
Selahattin Sayil, Lamar University
Nur Touba, University of Texas–Austin Syed Kamrul Islam, University of Tennessee Simon Y. Foo, Florida State University Rizwan Bashirullah, University of Florida
Wagdy Mahmoud, University of the District of Columbia
Azadeh Davoodi, University of Wisconsin
John Loomis, University of Dayton
The editorial staff of McGraw-Hill has again been helpful and supportive throughout the entire revision project. We especially acknowledge the contributions of Mr. Raghu Srinivasan, Ms. Darlene Schuller, Ms. Lisa Bruodt, and Mr. Vincent Bradshaw, for their valuable assistance during all stages of this complex project, and for their patience and persistence. We truly enjoyed sharing this experience with the entire McGraw-Hill team.
Finally, we would like to acknowledge the support from our families, Myoung-A (Mia), Jennifer, and Jeffrey Kang and Victoria Tung, An＆#305;l and Ebru Leblebici, and Mi-Soon Choi, Minjin, and Doyeon Kim, for tolerating many of our physical and mental absences while we worked on the fourth edition of this textbook, and for pro- viding us invaluable encouragement throughout the project.

Sung-Mo (Steve) Kang Yusuf Leblebici Chluwoo Kim
Daejeon, Korea Lausanne, Switzerland Seoul, Korea
August 2013 August 2013 August 2013
 
前 言

互补金属氧化物半导体（CMOS）数字集成电路是当今信息时代一种领先技术。由于具有低功耗、大噪声容限以及易于设计等固有的特点，CMOS 集成电路在开发研制随机存储器（RAM）、微处理器、数字信号处理（DSP）和专用集成电路（ASIC）芯片方面得到了广泛的应用。随着在移动计算平台、可穿戴设备、智能手机和多媒体系统等芯片开发方面对于低功耗、低噪声电子系统日益增长的需求，CMOS 电路的广泛应用将持续增长。
CMOS 集成电路涉及的领域非常广泛，通常分为数字CMOS电路和模拟CMOS电路两类。本书将集中讨论 CMOS 数字集成电路。然而需要指出的是：随着纳米制作工艺、极低的工作电压和 GHz 级工作频率带来的挑战，经典的数字CMOS电路设计与模拟CMOS电路设计的界限已渐趋模糊。因此，作者将试图从“模拟”的角度来分析和设计数 字 CMOS 电路，例如用器件和电路的模拟及连续特性来实现数字化功能。
作者在20世纪90年代初期即计划撰写本书，当时两位主要作者正在从事本科及研究生的数字集成电路基础教学。在美国伊利诺伊大学厄巴纳-香槟分校任教期间，在高年级工程技术选修课（即ECE382—大规模集成电路设计）教学中作者曾尝试选用已有的教材，然而老师和同学们一致反映需要一本深入讨论CMOS逻辑电路的全新教材，因此作者通过整理多年的课堂讲义开始编撰本书。从1993年起，作者在美国伊利诺伊大学厄巴纳-香槟分校、土耳其伊斯坦布尔科技大学、美国伍斯特理工学院、瑞士联邦工学院使用了这些新版的讲义。从广大同学、同行及审阅者的好评中，我们得到了极大的肯定和鼓舞。 于1995年底出版了《CMOS 数字集成电路—分析与设计》的第一版。
在第一版出版后不久，使用本书的众多师生提出了许多建设性的意见，作者迫切感到本书有待修订。作者对低功耗电路的设计、高速电路设计中的互连线问题、深亚微米电路设计等问题进行了修改和补充，并针对存储电路的新发展提供了众多更为精确有效的处理方法。在CMOS数字电路这个发展异常迅速的领域中，一本教科书只有通过不断修订，及时反映当今的技术发展水平，才能保证具有高的学术水平。基于这种认识，作者对本书不断地进行修订，先后于1998年、2002年出版了第二版和第三版，以反映技术水平和电路设计实践的最新发展。
从2002年本书第三版发行到现今的11年里，CMOS数字集成电路领域一直以越来越快的速度发展。纳米科技的出现以及集成大量功能模块的片上系统的广泛应用给CMOS数字集成电路的设计方式带来了巨大且亟需应对的改变。因此我们认为仅对内容进行增加修订已经不能满足本教材下一版本的要求了，而是需要对几乎所有章节进行全面重写。我们的作者团队加入了一位重要成员，来自韩国高丽大学的 Chulwoo Kim 教授。我们一起对本教材进行了大量修订。本书的第四版终于在付出艰辛努力后诞生了。本书可作为高年级本科生和一年级研究生的教材，也可供从事集成电路设计、数字设计、VLSI 等领域的工程师参考。数字集成电路设计正在持续高速地发展，作者也竭尽全力对本书所涵盖的内容提供最新的资料。
本书共分15章，依据作者的教学经验，在一学期内教授本书所有内容略显局促，因此推荐按照如下计划授课：在面向本科生的教学中，用一学期的时间来讲授第1章至第10章有关 CMOS 数字集成电路的内容。如时间允许，还可有选择地讲授第11章“低功耗 CMOS逻辑电路”、第12章“算术组合模块”和第13章“时钟电路与输入输出电路”的内容。本书也可安排为两学期讲授，可以对后面章节中的新问题进行详细的探讨。在面向研究生的教学中，本书的全部章节可安排在一个学期内讲授。
本书的第1章至第18章详细讨论MOS晶体管及其相关特性、静态和动态工作原理与分析以及基本反相器电路的设计、组合逻辑电路及时序逻辑电路的结构与工作原理。第四版第1章的内容有大量扩充，将详细介绍一些VLSI的设计方法。由于本书的前半部分主要讨论的是与数字VLSI及ASIC设计相关的一些数字IC设计方法，作者认为有必要在本书的开头加以说明。第6章深入讨论芯片上的互连线模型及互连线上的延迟时间计算，并将完整介绍数字集成电路的开关特性。第9章单独介绍应用于达到领先水平的VLSI芯片上的动态逻辑电路。第10章在内容和表达形式方面都做了全面的修改，深入地介绍许多达到当今领先水平的半导体存储电路。由于低功耗电路设计的重要性日益增加，作者在第11章将致力于低功耗 CMOS 逻辑电路的讨论，全面覆盖了低功耗大规模数字集成电路的设计方法和实例。第12章介绍关键算数运算模块，并重点介绍高性能多位加法器和乘法器。第13章将对时钟电路和芯片的I/O设计做详细介绍。对如 ESD 保护电路、时钟分配、时钟缓冲及闩锁效应等一系列不可忽视的问题也给出了详细的讨论。最后，第14章和第15章分别讨论电路的可制造性设计和可测试性设计这两个重要问题。 作者曾就本书中的nMOS电路进行了长篇幅的讨论。从教学的角度来看，对nMOS电路进行一些介绍是有益的。为了强调广泛应用于数字电路设计的负载的概念，第5章介绍了基本的电阻型负载和伪nMOS反相器电路以及与其对应的CMOS电路，并在第7章介绍伪nMOS逻辑门（与非/或非）。
本书的教师资源包括习题解答和PPT，学生资源包括Cadence设计教程和本书彩图。
教师资源申请邮箱：te_service@phei.com.cn。学生资源可在www.mhhe.com/kang或华信教育资源网（www.hxedu.com.cn）下载。